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1 ? fn8112.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005-2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x40020, x40021 dual voltage monitor with integrated cpu supervisor and system battery switch features ? dual voltage detection and reset assertion ?three standard reset threshold settings (4.6v/2.9v, 4.6v/2.6v, 2.9v/1.6v) ?v trip2 programmable down to 0.9v ?adjust low voltage reset threshold voltages using special programming sequence ?reset signal valid to v cc = 1v ?monitor two voltages or detect power fail ? battery switch backup ?v out : 5ma to 50ma from v cc ; 250a from v batt ? fault detection register ? selectable power-on reset timeout (0.05s, 0.2s, 0.4s, 0.8s) ? selectable watchdog timer interval (25ms, 200ms, 1.4s, off) ? debounced manual reset input ? low power cmos ?25a typical standby current, watchdog on ?6a typical standby current, watchdog off ?1a battery current in backup mode ? 400khz 2-wire interface ? 2.7v to 5.5v power supply operation ? available packages ?14-lead soic, tssop ? monitor voltages: 5v to 1.6v ? memory security ? pb-free plus anneal available (rohs compliant) applications ? communications equipment ?routers, hubs, switches ?disk arrays ? industrial systems ?process control ?intelligent instrumentation ? computer systems ?desktop computers ?network servers x40020, x40021 description the x40020 combines power-on reset control, watch- dog timer, supply voltage supervision, and secondary supervision, and manual reset, in one package. this combination lowers system cost, reduces board space requirements, and in creases reliability. applying voltage to v cc activates the power-on reset circuit which hol ds reset/reset active for a period of time. this allows the power supply and system oscilla- tor to stabilize before the pr ocessor can execute code. block diagram standard v trip1 level standard v trip2 , level suffix 4.6v (1%) 2.9v(1.7%) -a 4.6v (1%) 2.6v (2%) -b 2.9v(1.7%) 1.6v (3%) -c see ?ordering information? for more details for custom settings, call intersil. v2fail wdo mr lowline reset reset x40020 x40021 + - v2 monitor logic v trip2 fault detection register status register data register command decode test & control logic power-on, manual reset low voltage reset generation v cc monitor logic v2mon sda wp scl v cc (v1mon) watchdog and reset logic system switch battery v batt v out batt-on + - v trip1 v out v out v out data sheet may 17, 2006
2 fn8112.1 may 17, 2006 ordering information part number* with reset part marking part number* with reset part marking monitored v cc supplies v trip1 range (mv) v trip2 range (mv) temp. range (c) package pkg. dwg. # x40020s14-c x40020s c x40021s14-c x40021s c 1.6 to 3.6 2.9 50 1.6 50 0 to 70 14 ld soic (150 mil) mdp0027 x40020s14i-c x40020s ic x40021s14i-c x40021s ic -40 to +85 14 ld soic (150 mil) mdp0027 x40020v14-c x4002 0vc x40021v14-c x4002 1vc 0 to 70 14 ld tssop (4.4mm) m14.173 x40020v14i-c x4002 0vic x40021v14i-c x4002 1vic -40 to +85 14 ld tssop (4.4mm) m14.173 x40020s14-b x40020s b x40021s14-b x40021s b 2.6 to 5.5 4.6 50 2.6 50 0 to 70 14 ld soic (150 mil) mdp0027 x40020s14z-b (note) x40020s zb x40021s14z-b (note) x40021s zb 0 to 70 14 ld soic (150 mil) (pb-free) mdp0027 x40020s14i-b x40020s ib x40021s14i-b x40021s ib -40 to +85 14 ld soic (150 mil) mdp0027 x40020s14iz-b (note) x40020s zib x40021s14iz-b (note) x40021s zib -40 to +85 14 ld soic (150 mil) (pb-free) mdp0027 x40020v14-b x4002 0vb x40021v14-b x4002 1vb 0 to 70 14 ld tssop (4.4mm) m14.173 x40020v14z-b (note) x4002 0vzb x40021v14z-b (note) x4002 1vzb 0 to 70 14 ld tssop (4.4mm) (pb-free) m14.173 x40020v14i-b x4002 0vib x40021v14i-b x4002 1vib -40 to +85 14 ld tssop (4.4mm) m14.173 X40020V14IZ-B (note) x4002 0vzib x40021v14iz-b (note) x4002 1vzib -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 x40020s14-a x40020s a x40021s14-a x40021s a 2.9 to 5.5 2.9 50 0 to 70 14 ld soic (150 mil) mdp0027 x40020s14z-a (note) x40020s za x40021s14z-a (note) x40021s za 0 to 70 14 ld soic (150 mil) (pb-free) mdp0027 x40020s14i-a x40020s ia x40021s14i-a x40021s ia -40 to +85 14 ld soic (150 mil) mdp0027 x40020s14iz-a (note) x40020s zia x40021s14iz-a (note) x40021s zia -40 to +85 14 ld soic (150 mil) (pb-free) mdp0027 x40020v14-a x4002 0va x40021v14-a x4002 1va 0 to 70 14 ld tssop (4.4mm) m14.173 x40020v14z-a (note) x4002 0vza x40021v14z-a (note) x4002 1vza 0 to 70 14 ld tssop (4.4mm) (pb-free) m14.173 x40020v14i-a x4002 0via x40021v14i-a x4002 1via -40 to +85 14 ld tssop (4.4mm) m14.173 x40020v14iz-a (note) x4002 0vzia x40021v14iz-a (note) x4002 1vzia -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 *add "t1" suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. x40020, 40021
3 fn8112.1 may 17, 2006 low v cc detection circuitry protects the user?s system from low voltage conditions, resetting the system when v cc falls below the minimum v trip1 point. reset/reset is active until v cc returns to proper operating level and stabilizes . a second voltage moni- tor circuit tracks the unregul ated supply to provide a power fail warning or monitors different power supply voltage. three common low voltage combinations are available. however, intersil?s unique circuits allows the threshold for either voltage monitor to be repro- grammed to meet specific system level requirements or to fine-tune the threshold for applications requiring higher precision. a manual reset input provides debounce circuitry for minimum reset component count. a battery switch circuit compares v cc with v batt input and connects v out to whichever is higher. this pro- vides voltage to external sram or other circuits in the event of main power failure. the x40020/21 can drive 50ma from v cc to 250a from v batt . the device only switches to v batt when v cc drops below the low v cc voltage threshold and v batt . the watchdog timer provides an independent protec- tion mechanism for microcontrollers. when the micro- controller fails to restart a timer within a selectable time out interval, the device activates the wdo signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the device features an 2-wire interface and software protocol allowing operation on a two-wire bus. the device utilizes intersil?s proprietary direct write ? cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. pin configuration v batt v ss v cc sda scl 3 2 4 1 12 13 11 14 lowline wdo reset 7 6 5 8 9 10 v2mon mr wp 3 2 4 1 12 13 11 14 7 6 5 8 9 10 v out batt-on v2fail v batt v cc sda scl wp v out batt-on v ss lowline wdo reset v2mon mr v2fail x40020 x40021 14-pin soic, tssop 14-pin soic, tssop pin description pin name function 1v2fail v2 voltage fail output. this open drain output goes low when v2mon is less than v trip2 and goes high when v2mon exceeds v trip2 . there is no power-up reset delay circuitry on this pin. 2v2mon v2 voltage monitor input. when the v2mon input is less than the v trip2 voltage, v2fail goes low. this input can monitor an unregulated power su pply with an external resistor divider or can monitor a second power supply with no external components. connect v2mon to v ss or v cc when not used. 3lowline early low v cc detect. this open drain output signal goes low when v cc < v trip1 . when v cc > v trip1 , this pin is pulled high with the use of an external pull up resistor. 4wdo wdo output. wdo is an active low, open drain output which goes active whenever the watchdog timer goes active. 5mr manual reset input. pulling the mr pin low initiates a system reset. the reset/reset pin will remain high/low until the pin is released and for the t purst thereafter. it has an internal pull up resistor. 6 reset / reset reset output. (x40021) this open drain pin is an active low output which goes low whenever v cc falls below v trip1 voltage or if manual reset is asserted. this output stays active for the pro- grammed time period (t purst ) on power-up. it will also stay active until manual reset is released and for t purst thereafter. reset output. (x40020) this pin is an active high open drain output which goes high whenever v cc falls below v trip1 voltage or if manual reset is asserted. this output stays active for the pro- grammed time period (t purst ) on power-up. it will also stay active until manual reset is released and for t purst thereafter. x40020, 40021
4 fn8112.1 may 17, 2006 7v ss ground 8sda serial data. sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drain or open collector outputs. this pin requires a pull up resistor and the input buffer is always active (not gated). watchdog input. a high to low transition on the sda (while scl is toggled from high to low and followed by a stop condition) restarts the watchdog timer. the absence of this transition within the watchdog time out period results in wdo going active. 9scl serial clock. the serial clock controls the serial bus timing for data input and output. 10 wp write protect. wp high prevents writes to any location in the device (including all the registers). it has an internal pull down resistor. (>10m ? typical) 11 v batt battery supply voltage. this input provides a backup supply in the event of a failure of the primary v cc voltage. the v batt voltage typically provides the supply voltage necessary to maintain the contents of sram and also powers the internal logic to ?stay awake.? if the battery is not used, connect v batt to ground. 12 v out output voltage. (v) v out = v cc if v cc > v trip1 . if v cc < v trip1 then v out = v cc if v cc > v batt + 0.03v else v out = v batt (ie if v cc < v batt ? 0.03v) note: there is hysteresis around v batt 0.03v point to avoid oscillation at or near the switchover voltage. a capacitance of 0.1f must be connected to v out to ensure stability. 13 batt-on battery on. this cmos output goes high when the v out switches to v batt and goes low when v out switches to v cc . it is used to drive an external pnp pass transistor when v cc = v out and current requirements are greater than 50ma. the purpose of this output is to drive an external transistor to get higher operating currents when the v cc supply is fully functional. in the event of a v cc failure, the battery voltage is applied to the v out pin and the external transistor is turned off. in this ?backup condition,? the battery only needs to supply enough voltage and current to keep sram devices from losing their data?there is no communication at this time. 14 v cc supply voltage pin description (continued) pin name function x40020, 40021
5 fn8112.1 may 17, 2006 principles of operation power-on reset applying power to the x40020/21 activates a power- on reset circuit that pulls the reset/reset pins active. this signal provides several benefits. ? it prevents the system micr oprocessor from starting to operate with insufficient voltage. ? it prevents the processor from operating prior to sta- bilization of the oscillator. ? it allows time for an fpga to download its configura- tion prior to initialization of the circuit. ? it prevents communication to the eeprom, greatly reducing the likelihood of data corruption on power-up. when v cc exceeds the device v trip1 threshold value for t purst (selectable) the circ uit releases the reset (x40021) and reset (x40020) pin allowing the system to begin operation. figure 1. connecting a manual reset push-button manual reset by connecting a push-but ton directly from mr to ground, the designer adds manual system reset capa- bility. the mr pin is low while the push-button is closed and reset/reset pin remains low for t purst or till the push-button is released and for t purst thereafter. a weak pull up resistor is connected to the mr pin. low voltage v1 monitoring during operation, the x40020/21 monitors the v cc level and asserts reset if supply voltage falls below a preset minimum v trip1 . the reset signal prevents the microprocessor from operating in a power fail or brownout condition. the v1fail signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip1 for t purst . low voltage v2 monitoring the x40020/21 also monitors a second voltage level and asserts v2fail if the voltage falls below a preset mini- mum v trip2 . the v2fail signal is either ored with reset to prevent the microprocessor from operating in a power fail or brownout condition or used to interrupt the microprocessor with notification of an impending power failure. the v2fail signal remains active until the v cc drops below 1v (v cc falling). it also remains active until v2mon returns and exceeds v trip2 . v2mon voltage monitor is powered by v out. if v cc and v batt go away, v2mon cannot be monitored. figure 2. two uses of multiple voltage monitoring watchdog timer the watchdog timer circuit monitors the microprocessor activity by monitoring the sda and scl pins. a standard read or write sequence to any slave address byte restarts the watchdog timer and prevents the wdo sig- nal to go active. a minimum sequence to reset the watchdog timer requires four microprocessor instructions namely, a start, clock low, clock high and stop. the state of two nonvolatile control bits in the status register determine the watchdog timer period. the microproces- sor can change these watchdog bits by writing to the x40020/21 control register (also refer to page 21). mr system reset manual reset x40020 reset unreg. supply v cc 5v reg v2mon x40020 resistors selected so 3v appears on v2mon when unregulated supply reaches 6v. unreg. supply v cc x40021 reset v2fail system v out reset reset v2fail v out system reset notice: no external components required to monitor two voltages. r r v2mon 5v reg 3v reg x40020, 40021
6 fn8112.1 may 17, 2006 figure 3. v tripx set/reset conditions figure 4. watchdog restart v1 and v2 threshold program procedure (optional) the x40020/21 is shipped with standard v1 and v2 threshold (v trip1, v trip2 ) voltages. these values will not change over normal operating and storage conditions. however, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the x40020 trip points may be adjusted. the procedure is described below, and uses the application of a high voltage control signal. setting a v tripx voltage (x = 1, 2) there are two procedures used to set the threshold volt- ages (v tripx ), depending if the threshold voltage to be stored is higher or lower than the present value. for example, if the present v tripx is 2.9 v and the new v tripx is 3.2 v, the new voltage can be stored directly into the v tripx cell. if however, the new setting is to be lower than the present setting, then it is necessary to ?reset? the v tripx voltage before setting the new value. setting a higher v tripx voltage (x = 1, 2) to set a v tripx threshold to a new voltage which is higher than the present threshold, the user must apply the desired v tripx threshold voltage to the corresponding input pin (vcc(v1mon) or v2mon). then, a program-ming voltage (vp) must be applied to the wdo pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h, followed by the byte address 01h for v trip1 , and 09h for v trip2 , and a 00h data byte in order to program v tripx . the stop bit following a valid write operation initiates the programming sequence. pin wdo must then be brought low to complete the operation. to check if the v tripx has been set, set vxmon to a value slightly greater than v tripx (that was previously set). slowly ramp down vxmon and observe when the corresponding outputs (lowline and v2fail ) switch. the voltage at which this occurs is the v tripx (actual). c ase a now if the desired v tripx is greater than the v tripx (actual), then add the difference between v tripx (desired) - v tripx (actual) to the original v tripx desired. this is your new v tripx that should be applied to vxmon and the whole sequence should be repeated again (see figure 5). c ase b now if the v tripx (actual), is higher than the v tripx (desired), perform the reset sequence as described in the next section. the new v tripx voltage to be applied to vxmon will now be: v tripx (desired) - (v tripx (actual) - v tripx (desired)). note: 1. this operation does not corrupt the memory array. 2. set v cc = 5v, when v trip2 is being pro- grammed setting a lower v tripx voltage (x = 1, 2) in order to set v tripx to a lower vo ltage than the present value, then v tripx must first be ?reset? accord- ing to the procedure described below. once v tripx has been ?reset?, then v tripx can be set to the desired voltage using the procedure described in ?setting a higher v tripx voltage?. v cc /v2mon v tripx v p t wc a0h 0 7 70 7 0 scl wdo sda (x = 1, 2) 00h scl sda .6s 1.3s wdt reset start stop x40020, 40021
7 fn8112.1 may 17, 2006 resetting the v tripx voltage to reset a v tripx voltage, apply the programming volt- age (vp) to the wdo pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h followed by the byte address 03h for v trip1 and 0bh for v trip2 , followed by 00h for the data byte in order to reset v tripx . the stop bit following a valid write operation in itiates the programming sequence. pin wdo must then be brought low to complete the operation. after being reset, the value of v tripx becomes a nominal value of 1.7v or lesser. note: this operation does not corrupt the registers. system battery switch as long as v cc exceeds the low voltage detect thresh- old v trip , v out is connected to v cc through a 5 ? (typi- cal) switch. when the v cc has fallen below v1 trip , then v cc is applied to v out if v cc is or equal to or greater than v batt - 0.03v. when v cc drops to less than v batt - 0.03v, then v out is connected to v batt through an 80 ? (typical) switch. v out typically supplies the system static ram voltage, so the switchover circuit operates to protect the contents of the static ram dur- ing a power failure. typically, when v cc has failed, the srams go into a lower power state and draw much less current than in their active mode. when v cc returns, v out switches back to v cc when v cc exceeds v batt + 0.03v. there is a 60mv hysteresis around this battery switch threshold to prev ent oscillations between sup- plies. while v cc is connected to v out the batt-on pin is pulled low. the signal can drive an external pnp tran- sistor to provide additional current to the external circuits during normal operation. operation the device is in normal operation with v cc as long as v cc > v trip1 . it switches to the battery backup mode when v cc goes away. control register the control register provides the user a mechanism for changing the block lock and watchdog timer settings. the block lock and watchdog timer bits are nonvolatile and do not change when power is removed. the control register is accessed with a special pream- ble in the slave byte (1011) and is located at address 1ffh. it can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. prior to writing to the control register, the wel and rwel bits must be set using a two step process, with the whole sequence requiring 3 steps. see "writing to the control registers" on page 8. the user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores wd1, wd0, pup1, and pup0. the x40020 will not acknowl- edge any data bytes written afte r the first byte is entered. the state of the control register can be read at any time by performing a random read at address 01fh, using the special preamble. only one byte is read by each register read operation. the master should supply a stop condi- tion to be consistent with the bus protocol, but a stop is not required to end this operation. rwel: register write en able latch (volatile) the rwel bit must be set to ?1? prior to a write to the control register. figure 5. sample v trip reset circuit condition mode of operation v cc > v trip1 normal operation v cc > v trip1 & v batt = 0 normal operation without battery backup capability 0 v cc v trip1 and v cc < v batt battery backup mode; reset signal is asserted. no communica- tion to the device is allowed. 76543210 pup1 wd1 wd0 0 0 rwel wel pup0 1 6 2 7 14 13 9 8 x40020 v trip1 adj. v p reset 4.7k sda scl c adjust run v2fail v trip2 adj. x40020, 40021
8 fn8112.1 may 17, 2006 figure 6. v tripx set/reset sequence (x = 1, 2) wel: write enable latch (volatile) the wel bit controls the access to the memory and to the register during a write operation. this bit is a vola- tile latch that powers up in the low (disabled) state. while the wel bit is low, writes to any address, including any control regi sters will be ignored (no acknowledge will be issued after the data byte). the wel bit is set by writing a ?1? to the wel bit and zeroes to the other bits of the control register. once set, wel remains set unt il either it is reset to 0 (by writing a ?0? to the wel bit and zeroes to the other bits of the control register ) or until the part powers up again. writes to the wel bit do not cause a high volt- age write cycle, so the device is ready for the next operation immediately af ter the stop condition. v tripx programming apply v cc and voltage decrease v x actual v tripx - desired v tripx done set higher v x sequence error < mde ? | error | < | mde | yes no error > mde + > desired v tripx to v x desired present value v tripx < execute no yes execute v tripx reset sequence set v x = desired v tripx new v x applied = old v x applied + | error | new v x applied = old v x applied - | error | execute reset v tripx sequence output switches? note: x = 1, 2 let: mde = maximum desired error vx = v cc , vxmon mde + desired value mde ? acceptable error range error = actual - desired x40020, 40021
9 fn8112.1 may 17, 2006 bp: block protect bit (nonvolatile) the block protect bits bp determines which blocks of the array are write protected. a write to a protected block of memory is ignored. the block protect bit will prevent write operations to half the array segment. pup1, pup0: power-up bits (nonvolatile) the power-up bits, pup1 and pup0, determine the t purst time delay. the nominal power-up times are shown in the following table. wd1, wd0: watchdog timer bits the bits wd1 and wd0 control the period of the watchdog timer. the options are shown below. writing to the co ntrol registers changing any of the nonvolatile bits of the control and trickle registers requir es the following steps: ? write a 02h to the control register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation pre- ceded by a start and ended with a stop). ? write a 06h to the control register to set the register write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation proceeded by a start and ended with a stop). ? write a one byte value to the control register that has all the control bits set to the desired state. the control register can be represented as qxy 0 001 r in binary, where xy are the wd bits, and qr are the power-up bits. this operation proceeded by a start and ended with a stop bit. since this is a nonvolatile write cycle it will take up to 10ms to complete. the rwel bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. if bit 2 is set to ?1? in this third step ( qxy 0 011 r ) then the rwel bit is set, but the wd1, wd0, pup1, and pup0, bits remain unchanged. writing a second byte to the control register is not allowed. doing so aborts the write operation and returns a nack. ? a read operation occurring between any of the previ- ous operations will not inte rrupt the regi ster write operation. ? the rwel bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. to illustrate, a sequ ence of writes to the device con- sisting of [02h, 06h, 02h] will reset all of the nonvola- tile bits in the control register to 0. a sequence of [02h, 06h, 06h] will leave the nonvolatile bits unchanged and the rwel bit remains set. note: 1. t purst is set to 200ms as factory default. 2. watchdog timer bits are shipped disabled. fault detection register (fdr) the fault detection register provides the user the status of what causes th e system reset active. the manual reset fail, watchdog timer fail and three low voltage fail bits are volatile. the fdr is accessed with a special preamble in the slave byte (1011) and is located at address 0ffh. it can only be modified by performing a byte write opera- tion directly to the addres s of the register and only one data byte is allowed for each register write operation. there is no need to set the wel or rwel in the con- trol register to access this fault detection register. bp protected addresses (size) memory array lock 0 none none 1 100h - 1ffh (256 bytes) upper half of memory array pup1 pup0 power-on reset delay ( t purst ) 0 0 50ms 0 1 200ms (default) 1 0 400ms 1 1 800ms wd1 wd0 watchdog time out period 0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled (factory default) 7 6543210 lv1f lv2f 0 wdf mrf 0 0 0 x40020, 40021
10 fn8112.1 may 17, 2006 figure 7. valid data changes on the sda bus at power-up, the fault detection register is defaulted to all ?0?. the system needs to initialize this register to all ?1? before the actual monitoring take place. in the event of any one of the monitored sources failed. the corresponding bits in the register will change from a ?1? to a ?0? to indicate the failure. at this moment, the system should perform a read to the register and noted the cause of the reset. after reading the register the system should reset the register back to all ?1? again. the state of the fault detection register can be read at any time by performing a random read at address 0ffh, using the special preamble. the fdr can be read by performing a random read at 0ffh address of the register at any time. only one byte of data is read by the register read operation. mrf, manual reset fail bit (volatile) the mrf bit will set to ?0 ? when manual reset input goes active. wdf, watchdog timer fail bit (volatile) the wdf bit will set to ?0? when wdo goes active. lv1f, low v cc reset fail bit (volatile) the lv1f bit will be set to ?0? when v cc (v1mon) falls below v trip1 . lv2f, low v2mon reset fail bit (volatile) the lv2f bit will be set to ?0? when v2mon falls below v trip2 . interface conventions the device supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this fam- ily operate as slaves in all applications. serial clock and data data states on the sda line can change only during scl low. sda state cha nges during scl high are reserved for indicating start and stop conditions. see figure 7. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the st art condition and will not respond to any command until this condition has been met. see figure 8. serial stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condi tion is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has rel eased the bus. see figure 8. scl sda data stable data change data stable x40020, 40021
11 fn8112.1 may 17, 2006 figure 8. valid start and stop conditions serial acknowledge acknowledge is a software convention used to indi- cate successful data transf er. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during t he ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. see figure 9. the device will respond wit h an acknowledge after recognition of a start condition and if the correct device identifier and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identifier and/or select bits are incorrect. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data . the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. serial write operations byte write for a write operation, the device requires the slave address byte and a word address byte. this gives the master access to any one of the words in the array. after receipt of th e word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, so the de vice will not respond to any requests from the master. the sda output is at high impedance. figure 9. acknowledge response from receiver scl sda start stop data output from data output from receiver 8 1 9 start acknowledge scl from master x40020, 40021
12 fn8112.1 may 17, 2006 figure 10. byte write sequence stops and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ack is sent, then the device will reset itself withou t performing the write. the contents of the arra y will not be effected. acknowledge polling the disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indi- cate the end of the master?s byte load operation, the device initiates the inte rnal high voltage cycle. acknowledge polling can be initiated immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the high voltage cycle then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. see figure 11. serial read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address byte is set to one. figure 11. acknowledge polling sequence s t a r t s t o p slave address byte address data a c k a c k a c k sda bus signals from the slave signals from the master 0 ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes high voltage cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes x40020, 40021
13 fn8112.1 may 17, 2006 read operation prior to issuing the slave address byte with the r/w bit set to one, the master must first perform a ?dummy? write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address by tes. after acknowledging receipts of the word address bytes, the master immedi- ately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. see figure 12 for the address, acknowl- edge, and data transfer sequence. serial device addressing memory address map cr, control register, cr7: cr0 address: 1ff hex fdr, fault detectionregister, fdr7: fdr0 address: 0ff hex slave address byte following a start condition, the master must output a slave address byte. this byte consists of several parts: ? a device type identifier that is always ?1011? when accessing the control register and fault detection register. ? two bits of ?0?. ? one bit that becomes the msb of the memory address x 4 . ? last bit of the slave command byte is a r/w bit. the r/w bit of the slave address byte defines the oper- ation to be performed. when the r/w bit is a one, then a read operation is selected. a zero selects a write operation. see figure 13. figure 12. read sequence 0 slave address byte address a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master 101 0 0 1 11111111 x40020, 40021
14 fn8112.1 may 17, 2006 figure 13. slave address, word address, and data bytes word address the word address is either supplied by the master or obtained from an internal counter. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? the wel bit is set to ?0?. in this state it is not possi- ble to write to the device. ? sda pin is the input mode. ? reset/reset signal is active for t purst . data protection the following circuitry has been included to prevent inadverten t writes: ? the wel bit must be set to allow write operations. ? the proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. ? a three step sequence is required before writing into the control register to change watchdog timer or block lock settings. ? the wp pin, when held hi gh, prevents all writes to the array and all the register. general purpose memory control register fault detection register 1 1 0 0 1 1 0 1 a8 r/w word address slave byte 1 0 1011 0 0 0 0 0 0 r/w r/w general purpose memory control register fault detection register a7 1 a6 a5 a4 a1 a0 1 a3 a2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x40020, 40021
15 fn8112.1 may 17, 2006 absolute maximum ratings temperature under bias .................... -65c to +135c storage temperature ......................... -65c to +150c voltage on any pin with respect to v ss ...................................... -1.0v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10s) .................... 300c comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating con- ditions for extended periods ma y affect device reliability. recommended operating conditions *see ordering info temperature min. max. commercial 0c 70c industrial -40c +85c version chip supply voltage monitored voltages* -a or -b 2.7v to 5.5v 2.6 to 5.5v -c 2.7v to 5.5v 1.6v to 3.6v d.c. operating characteristics (over the recommended operating cond itions unless otherwise specified) symbol parameter min. typ. (5) max. unit test conditions i cc1 (1) active supply current ( v cc ) read (excludes i out ) 1.5 ma v il = v cc x 0.1 v ih = v cc x 0.9, f scl = 400khz i cc2 (1) active supply current ( v cc ) write non volatile memory (excludes i out ) 3.0 ma i sb1 (1)(7) standby current ( v cc ) ac (wdt off) 6 10 a v il = v cc x 0.1 vih = v cc x 0.9 f scl , f sda = 400khz i sb2 (2)(7) standby current ( v cc ) dc (wdt on) 25 30 a v sda = v scl = v cc others = gnd or v cc i batt1 (3)(7 ) v batt current (excludes i out )0.21av out = v cc i batt2 (7) v batt current (excludes i out ) (battery backup mode) 0.2 6 a v batt = 2.8v v out = open v out1 (7) output voltage (v cc > v batt + 0.03v or v cc > v trip1 ) v cc -0.05v v cc -0.5v vi out = 5ma v cc = (4.5-5.5v) i out = 50ma v cc = (4.5-5.5v) v out2 (7) output voltage (v cc < v batt - 0.03v and v cc < v trip1 ) {battery backup} v batt -0.2 v i out = 250a v olb output (batt-on) low voltage 0.4 v i ol = 3.0ma (4.5-5.5v) v ohb output (batt-on) high voltage v out -0.8 v i oh = -0.4ma (4.5-5.5v) v bsh (7) battery switch hysteresis (v cc < v trip1 ) 30 -30 mv power-up power-down i li input leakage current (scl, mr ,wp) 10 a v il = gnd to v cc i lo output leakage current (sda, v2fail , wdo , reset ) 10 a v sda = gnd to v cc device is in standby (2) v il (3) input low voltage (sda, scl, mr ,wp) -0.5 v cc x 0.3 v v ih (3) input high voltage (sda, scl, mr ,wp) v cc x 0.7 v cc + 0.5 v x40020, 40021
16 fn8112.1 may 17, 2006 notes: (1) the device enters the active state after any start, and re mains active until: 9 clock cycl es later if the device selec t bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. (2) the device goes into standby: 200ns after any stop, exc ept those that initiate a high voltage write cycle; t wc after a stop that initiates a high voltage cycle; or 9 clock cycles afte r any start that is not followed by the corre ct device select bits in the slave addre ss byte. (3) negative numbers indicate charging current, positive numbers indicate discharge current. (4) v il min. and v ih max. are for reference only and are not tested. (5) at 25c, v cc = 3v. (6) see ordering information for standard programming leve ls. for custom programming levels, contact factory. (7) based on characterization data. equivalent input circuit for vxmon (x = 1, 2) v hys (7) schmitt trigger input hysteresis ? fixed input level ? v cc related level 0.2 .05 x v cc v v v ol output low voltage (sda, reset/re- set , lowline , v2fail , wdo ) 0.4 v i ol = 3.0ma (2.7-5.5v) i ol = 1.8ma (2.4-3.6v) v cc supply v trip1 (6) v cc reset trip point voltage range 2.0 4.75 v 4.55 4.6 4.65 a, b version 2.85 2.9 2.95 c version t rpdl (7) v trip 1 to lowline 5s second supply monitor v trip2 (6) v2mon reset trip point voltage range 0.9 3.5 v 2.85 2.9 2.95 a version 2.55 2.6 2.65 b version 1.55 1.6 1.65 c version t rpd2 (7) v trip 2 to v2fail 5s d.c. operating characteristics (continued) (over the recommended operating cond itions unless otherwise specified) symbol parameter min. typ. (5) max. unit test conditions + ? v ref t rpdx = 5s worst case output vxmon r c ? v = 100mv ? v v ref x40020, 40021
17 fn8112.1 may 17, 2006 capacitance note: (1) this parameter is not 100% tested. equivalent a.c. output load circuit for v cc = 5v a.c. test conditions symbol table symbol parameter max. unit test conditions c out (1) output capacitance (sda, reset, reset /lowline , v2fail , wdo ) 8pf v out = 0v c in (1) input capacitance (scl, wp) 6 pf v in = 0v input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load 5v sda 30pf v2mon 4.6k ? reset 30pf 2.06k ? v2fail v out 4.6k ? 30pf wdo /lowline must be steady will be steady may change from low will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance waveform inp uts outputs x40020, 40021
18 fn8112.1 may 17, 2006 a.c. characteristics note: (1) cb = total capacitance of one bus line in pf. timing diagrams bus timing symbol parameter 400khz unit min. max. f scl scl clock frequency 400 khz t in pulse width suppression time at inputs 50 ns t aa scl low to sda data out valid 0.1 0.9 s t buf time the bus free before start of new transmission 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 s t dh data output hold time 50 ns t r sda and scl rise time 20 +.1cb (1) 300 ns t f sda and scl fall time 20 +.1cb (1) 300 ns t su:wp wp setup time 0.6 s t hd:wp wp hold time 0 s cb capacitive load for each bus line 400 pf t su:sto t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t r t dh t aa x40020, 40021
19 fn8112.1 may 17, 2006 wp pin timing write cycle timing nonvolatile write cycle timing note: (1) t wc is the time from a valid stop condition at the end of a writ e sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless ac knowledge polling is used. power fail timings symbol parameter min. typ. (1) max. unit t wc (1) write cycle time 5 10 ms t hd:wp scl sda in wp t su:wp clk 1 clk 9 slave address byte start scl sda t wc 8 th bit of last byte ack stop condition start condition v2mon v2fail t r t f t rpdx v rvalid lowline or v cc or v tripx t rpdx t rpdx t rpdl t rpdl t rpdl x = 1, 2 x40020, 40021
20 fn8112.1 may 17, 2006 reset/reset /mr timings low voltage and watchdog timings parameters (@25c, vcc = 5v) note: (1) based on characterization data. symbol parameters min. typ. max. unit t rpd1 (1) t rpdl v trip1 to reset /reset (power-down only) v trip1 to lowline 5s t lr (1) lowline to reset/reset delay (power-down only) [= t rpd1 -t rpdl ] 500 ns t rpd2 (1) v trip2 to v2fail 5s t purst power-on reset delay: pup1 = 0, pup0 = 0 pup1 = 0, pup0 = 1 (factory default) pup1 = 1, pup0 = 0 pup1 = 1, pup0 = 1 50 (1) 200 400 (1) 800 (1) ms ms ms ms t f v cc, v2mon fall time 20 mv / s t r v cc, v2mon rise time 20 mv / s v rvalid reset valid v cc 1v t md (1) mr to reset/ reset delay (activation only) 500 ns t in1 pulse width suppression time for mr 50 ns t wdo watchdog timer period: wd1 = 0, wd0 = 0 wd1 = 0, wd0 = 1 wd1 = 1, wd0 = 0 wd1 = 1, wd0 = 1 (factory default) 1.4 (1) 200 (1) 25 off s ms ms t rst1 watchdog reset time out delay wd1 = 0, wd0 = 0 wd1 = 0, wd0 = 1 100 200 300 ms t rst2 watchdog reset time out delay wd1=1, wd0=0 12.5 25 37.5 ms t rsp watchdog timer restart pulse width 1 s v cc v trip1 reset reset t purst t purst t r t f t rpd1 v rvalid mr t md x40020, 40021
21 fn8112.1 may 17, 2006 watchdog time out for 2-wire interface v tripx set/reset conditions < t wdo t rst wdo sda start t wdo t rst scl start t rsp wdt restart start sda scl minimum sequence to reset wdt clockin (0 or 1) scl sda v cc /v2mon (v tripx ) wdo t tsu t thd t vph t vps v p t wc t vpo a0h 0 7 70 7 sets v trip1 sets v trip2 *01h *09h *03h *0bh resets v trip2 resets v trip1 0 start * all others reserved 00h * x40020, 40021
22 fn8112.1 may 17, 2006 v trip1 , v trip2 programming specifications: v cc = 2.0-5.5v; temperature = 25c parameter description min. max. unit t vps wdo program voltage setup time 10 s t vph wdo program voltage hold time 10 s t tsu v tripx level setup time 10 s t thd v tripx level hold (stable) time 10 s t wc v tripx program cycle 10 ms t vpo program voltage off time before next cycle 1 ms v p programming voltage 15 18 v v tran1 v trip1 set voltage range 2.0 4.75 v v tran2 v trip2 set voltage range 0.9 3.5 v v tv v tripx set voltage variation after programming (0-75c). -25 +25 mv t vps wdo program voltage setup time 10 s v tripx programming parameters are periodically sampled and are not 100% tested. x40020, 40021
23 fn8112.1 may 17, 2006 x40020, 40021 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) tolerance notes a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. l 2/01 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
24 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8112.1 may 17, 2006 x40020, 40021 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 0 o 8 o 0 o 8 o - rev. 2 4/06

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